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Z8523010PEG
IXYS Zilog Z8523010PEG technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Factory Lead Time | 13 Weeks | |
| Mount | Through Hole | |
| Mounting Type | Through Hole | |
| Package / Case | 40-DIP (0.620, 15.75mm) | |
| Number of Pins | 40Pins | |
| Packaging | Tube | |
| Published | 2007 | |
| JESD-609 Code | e3 | |
| Pbfree Code | yes | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 40Terminations | |
| Terminal Finish | Matte Tin (Sn) | |
| Max Operating Temperature | 100°C | |
| Min Operating Temperature | -40°C | |
| Additional Feature | MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO | |
| HTS Code | 8542.31.00.01 | |
| Voltage - Supply | 4.5V~5.5V | |
| Terminal Position | DUAL | |
| Supply Voltage | 5V | |
| Terminal Pitch | 2.54mm | |
| Base Part Number | Z85230 | |
| Pin Count | 40 | |
| Operating Supply Voltage | 5V | |
| Power Supplies | 5V | |
| Temperature Grade | INDUSTRIAL | |
| Interface | Bus | |
| Operating Supply Current | 9mA | |
| Max Supply Current | 9mA | |
| uPs/uCs/Peripheral ICs Type | SERIAL IO/COMMUNICATION CONTROLLER, SERIAL | |
| Clock Frequency | 10MHz | |
| Boundary Scan | NO | |
| Low Power Mode | NO | |
| External Data Bus Width | 8 | |
| RAM (words) | 0 | |
| Number of Serial I/Os | 2Serial I/Os | |
| Data Transfer Rate-Max | 0.3125 MBps | |
| Communication Protocol | ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC | |
| Data Encoding/Decoding Method | NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER) | |
| Length | 52.325mm | |
| Height Seated (Max) | 4.24mm | |
| Width | 15.24mm | |
| Radiation Hardening | No | |
| RoHS Status | ROHS3 Compliant | |
| Lead Free | Lead Free |
Z8523010PEG
Download datasheets and manufacturer documentation for Z8523010PEG
- DatasheetsZ8523010PEG-Zilog-datasheet-129545.pdf Z8523010PEG-Zilog-datasheet-14121049.pdf
- PCN Assembly/OriginMult Dev Site Qual 20/Nov/2019
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