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PMDPB58UPE,115
Nexperia PMDPB58UPE,115 technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Factory Lead Time | 8 Weeks | |
| Surface Mount | YES | |
| Package / Case | 6-UDFN Exposed Pad | |
| Mounting Type | Surface Mount | |
| Number of Pins | 6Pins | |
| Transistor Element Material | SILICON | |
| Turn Off Delay Time | 41 ns | |
| Number of Elements | 2 Elements | |
| Published | 2012 | |
| Packaging | Tape & Reel (TR) | |
| Operating Temperature | -55°C~150°C TJ | |
| JESD-609 Code | e3 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 6Terminations | |
| Terminal Finish | Tin (Sn) | |
| Max Power Dissipation | 515mW | |
| Pin Count | 6 | |
| Configuration | SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE | |
| Operating Mode | ENHANCEMENT MODE | |
| Case Connection | DRAIN | |
| Turn On Delay Time | 7 ns | |
| FET Type | 2 P-Channel (Dual) | |
| Transistor Application | SWITCHING | |
| Rds On (Max) @ Id, Vgs | 67m Ω @ 2A, 4.5V | |
| Vgs(th) (Max) @ Id | 950mV @ 250μA | |
| Input Capacitance (Ciss) (Max) @ Vds | 804pF @ 10V | |
| Gate Charge (Qg) (Max) @ Vgs | 9.5nC @ 4.5V | |
| Rise Time | 15ns | |
| Drain to Source Voltage (Vdss) | 20V | |
| Fall Time (Typ) | 14 ns | |
| Continuous Drain Current (ID) | 3.6A | |
| Gate to Source Voltage (Vgs) | 8V | |
| Max Dual Supply Voltage | -20V | |
| Pulsed Drain Current-Max (IDM) | 14.4A | |
| FET Technology | METAL-OXIDE SEMICONDUCTOR | |
| FET Feature | Logic Level Gate | |
| RoHS Status | ROHS3 Compliant | |
| Radiation Hardening | No |
PMDPB58UPE,115
Download datasheets and manufacturer documentation for PMDPB58UPE,115
- PCN PackagingLogo 10/Dec/2016 Label Chg 12/Mar/2017
- DatasheetsPMDPB58UPE
- PCN Design/SpecificationPMDPB58UPE Datasheet Update 5/Nov/2015
- RohsStatementNXP-Semiconductors-company-12.pdf
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